Bus Interconnection & structure

BUS

A bus is a  communication pathway connecting two or more devices. A key characteristic of a bus is that it is a shared transmission medium. Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus. If two devices transmit during the same time period, their signals will overlap and become garbled. Thus, only one device at a time can successfully transmit.

Typically, a bus consists of multiple communication pathways, or lines. Each line is capable of transmitting signals representing binary 1 and binary 0. Over time, a sequence of binary digits can be transmitted across a single line. Taken together, several lines of a bus can be used to transmit binary digits simultaneously (in parallel).

For example, an 8-bit unit of data can be transmitted over eight bus lines. Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. A bus that connects major computer components (processor, memory, I/O) is called a system bus. The most common computer interconnection structures are based on the use of one or more system buses.

Bus Structure

A system bus consists, typically, of from about 50 to hundreds of separate lines. Each line is assigned a particular meaning or function. Although there are many different bus designs, on any bus the lines can be classified into three functional groups : data, address, and control lines.

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In addition, there may be power distribution lines that supply power to the attached modules. The data lines provide a path for moving data among system modules. These lines, collectively, are called the data bus. The data bus may consist of 32, 64, 128, or even more separate lines, the number of lines being referred to as the width of the data bus. Because each line can carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time. The width of the data bus is a key factor in determining overall system performance.

For example, if the data bus is 32 bits wide and each instruction is 64 bits long, then the processor must access the
memory module twice during each instruction cycle.

 

Address Line

The address lines are used to designate the source or destination of the data on the data bus. For example, if the processor wishes to read a word (8, 16, or 32 bits) of data from memory, it puts the address of the desired word on the address lines. Clearly, the width of the address bus determines the maximum possible memory

capacity of the system. Furthermore, the address lines are generally also used to address I/O ports. Typically, the higher-order bits are used to select a particular module on the bus, and the lower-order bits select a memory location or I/O port within the module. For example, on an 8-bit address bus, address 01111111 and below might reference locations in a memory module (module 0) with 128 words of memory, and address 10000000 and above refer to devices attached to an I/O module (module 1).

 

Control lines

The control lines are used to control the access to and the use of the data and address lines. Because the data and address lines are shared by all components, there must be a means of controlling their use. Control signals transmit both command and timing information among system modules. Timing signals indicate the validity of data and address information. Command signals specify operations to be performed.

Typical control lines include:

Memory write: Causes data on the bus to be written into the addressed location.
Memory read: Causes data from the addressed location to be placed on the bus.
I/O write: Causes data on the bus to be output to the addressed I/O port.
I/O read: Causes data from the addressed I/O port to be placed on the bus.
Transfer ACK: Indicates that data have been accepted from or placed on the bus.
Bus request: Indicates that a module needs to gain control of the bus.
Bus grant:Indicates that a requesting module has been granted control of the bus
Interrupt request: Indicates that an interrupt is pending
Interrupt ACK: Acknowledges that the pending interrupt has been recognized
Clock: Is used to synchronize operations
Reset: Initializes all modules

The operation of the bus is as follows. If one module wishes to send data to another, it must do two things:

(1) obtain the use of the bus, and  (2) transfer data via the bus.

If one module wishes to request data from another module, it must

(1)obtain the use of the bus, and

(2) transfer a request to the other module over the appropriate control and address lines. It must then wait for that second module to send the data.
Physically, the system bus is actually a number of parallel electrical conductors. In the classic bus arrangement, these conductors are metal lines etched in a card or board (printed circuit board). The bus extends across all of the system
components, each of which taps into some or all of the bus lines.

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